Algebraic models of correctness for abstract pipelines

We apply algebraic tools for modelling microprocessors to the specification, implementation, and verification of an abstract pipelined case study. We employ a model of time based on counting events by means of a clock. We model systems by iterated maps that evolve over time from some initial state. We define formal correctness conditions, and introduce the one-step theorems that can reduce the complexity of formal verification. The algebraic models provide: (i) modular descriptions of pipelined systems; (ii) equational correctness criteria; and (iii) equational specification and verification techniques for the design of pipelined systems applicable to a range of software systems.